A memory controller is incorporated in an arithmetic processing device (CPU chip) and controls memory access to a main memory in response to a memory access request from an arithmetic processor (CPU core).
Alternatively, the memory controller is provided between the arithmetic processing device (CPU chip) and main memory and controls memory access from the arithmetic processing device.
A double data rate (DDR) synchronous dynamic random access memory (SDRAM) has been widely used as the main memory. The DDR SDRAM receives a clock from a memory controller and returns a data strobe signal (referred to hereinbelow as “DQS signal”) generated on the basis of the clock and a data signal (referred to hereinbelow as “DQ signal”) synchronized with the rising edge and falling edge of the DQS signal to the memory controller. The memory controller also latches (or fetches) the H level of L level of the DQ signal by using the timing of the rising edge and falling edge of the DQS signal.
For example, in the DDR SDRAM regulated by the DDR3 and later standards, a memory controller 20 causes a clock CLK to propagate to a plurality of memory chips in a main memory 30 in daisy-chain connection. As a result, the phases of the DQS signals returned from the memory chips are spread and do not match.
Accordingly, it has been suggested to provide a variable delay circuit that delays a DQS signal and a DQ signal in a signal receiving circuit in the memory controller, set a delay amount of a DQS signal variable delay circuit such that the phase of the received DQS signal matches the phase of the standard internal clock, also set the same set delay amount in the DQ signal variable delay circuit, and artificially synchronize the phase of the DQ signal with the phase of the internal clock.